AMD Vivado Design Suite Reviews

I mainly use AMD Vivado Design Suite for creating designs for AMD's Zynq SoC FPGAs. I tried creating a video pipeline for a Zynq design on the Zybo ZC10 board to capture video coming from an IMX219 and display it on an HDMI monitor using AMD Vivado Design Suite. I use AMD Vivado Design Suite to generate bit streams for AMD's FPGAs, and it is the most user-friendly FPGA tool compared to its competitors' tools.

The best features of AMD Vivado Design Suite is that it is a mature tool with a very good GUI. The most fascinating feature is its block design feature, which allows me to add and drop various IPs from AMD Vivado Design Suite's IP catalog and create a block design for my video designs. That is the one feature that I find very interesting.

It is also very easy to source control AMD Vivado Design Suite projects using Git. The IP catalog is another valuable feature, and it is a very good tool that I install on all of my employees' project devices.

I think the build times in certain projects are an area for improvement. When the design gets bigger, the build times to generate the bitstream can take hours. The algorithm to generate the bitstream could be improved, and that is the only reason it is not a perfect 10 for me.

I have been using AMD Vivado Design Suite for almost four years now.

It is pretty much scalable; it depends on your size. If you have enough space to install the tool, then you can install it.

The customer support is very good for AMD Vivado Design Suite. I am happy with the AMD customer support available online. You get accurate responses to your queries from AMD customer support, and I am satisfied with that.

There is no other alternate for AMD's FPGA board.

I cannot comment on any of the AI capabilities of AMD Vivado Design Suite because I have not used that yet for my personal projects. I have not used any of the latest AI features available in AMD Vivado Design Suite. I would recommend AMD Vivado Design Suite for any new FPGA designer. I give this product a rating of 9.

My most appreciating and most fascinating project with AMD Vivado Design Suite was my final year project, which was video enhancing for better communication on an FPGA. For the IP integrations and our RTL designs, I have used AMD Vivado Design Suite. I have also made many projects on cryptography, on MUXes, and on AR and VR, but my most major project is my final year project.

The project with AMD Vivado Design Suite is a driven video enhancement system. The goal is to transmit a low resolution, such as 240p, and enhance it to 3x, 720p, making the pixels more robust and accurate for about seven times to the original video I got. I have used FSRCNN, which is custom-made. I have not gotten it from any website. I made it myself. The project focuses on improving video quality while reducing transmission bandwidth requirements. Currently, I have developed and trained the CNN model in Python and am working on understanding its optimization. I have implemented all the components, including making IPs of my CNN model in AMD Vivado Design Suite, working with GPUs, making reference files, and making a chip of my FPGA project, which is video enhancing, so that it gets the enhanced image of 480p.

AMD Vivado Design Suite played a major role in FPGA integration. It provided a complete design flow of RTL development, bitstream generation, synthesizing the hardware design, performing implementation, analyzing timing, and verifying the timing diagram. One of the most important roles was that I got the IP of my CNN, but I had to integrate it with all the other components including Artix-7, interconnects, DMAs, and other components. I used those components.

The most important and valuable task of AMD Vivado Design Suite was its optimization. For example, if I got an FPGA board of Artix-7 20T, and I was facing the same problem, I got lots of DSPs, about 220 DSPs, but when I synthesized the program, the DSPs went out of the range. They demanded 300 flip-flops, about 80 above its maximum range it can reach. I found an option in AMD Vivado Design Suite where I can easily degrade and optimize my code so that it would get for about 220, less than 220 DSPs, so that they could be utilized even better.

The best feature AMD Vivado Design Suite offers in my experience is its automatic optimization. I can optimize things, including flip-flops and timing. For example, if I am working on an RTOS project and I want real-time performance, it must be a timing issue. AMD Vivado Design Suite provides me an automated, real-time timing diagram, and that could fix any issues in the RTL design that could affect the timing.

AMD Vivado Design Suite can be improved in some of its components. For example, if I want to do something on my Artix-7 or any PS side, I need to plan for three or four attempts and then I find the solution. I think it can be improved by just a bit more help, and the integration of AI is a must. It must tell me that I need to make this correct or that correct.

I have been using AMD Vivado Design Suite for about two years.

This automation in AMD Vivado Design Suite has saved me a lot of time. For example, as I was working on my FPGA Final Year Project (FYP), and it was pretty much extensive and hard, that optimization design feature really helped me a lot.

AMD Vivado Design Suite could be decomposed into many little parts, for example, in seconds. I can exactly view where the hysteresis loss is happening and where the signal is losing its hold.

AMD Vivado Design Suite has positively impacted my organization. I usually use AMD Vivado Design Suite. It really helped me in my studies and research.

Using AMD Vivado Design Suite has helped me personally be more productive and improve the quality of my work. I would rate this product an 8 out of 10.

I primarily work with FPGAs, specifically AMD and Xilinx FPGAs, so I use AMD Vivado Design Suite for both SOC-based software design as well as hardware design, which goes on to the fabric, and I use their HLS tools as well.

I have been working on a machine learning-based accelerator design on an FPGA called the A-LINX VD200, which is basically a Versal-based SOC and FPGA on a single chip. I have used that to design my software to use the accelerator that I designed on the FPGA. The software which runs on the CPU that is present on the Versal device runs some algorithm; in my case, it is a simple matrix multiplication, and it offloads the instructions to the accelerator that I designed on the FPGA part. I have designed this using AMD Vivado Design Suite.

One other specific use case that picked my interest was exploring DPI-C based emulation environments using AMD Vivado Design Suite. I have a project that I have been working on for a while wherein I was trying to design a mock device for FPGA for the JTAG protocol. I envision having a mock that acts as a JTAG device, developed in C++, and I would like to use this model and connect it with my protocol analyzer, which is basically an RTL code that I dumped onto the FPGA. I have an RTL code and I want to have an environment where my design talks to the mock, the C++ mock. I have been trying to use the DPI-C based communication between the SystemVerilog and C++ module in AMD Vivado Design Suite, and I am primarily exploring the XSIM capabilities to do this using CLI. This has been a unique workflow that I have been working on lately.

If people are working on FPGA design, AMD Vivado Design Suite is the one go-to tool that I would recommend for everyone. It is very user-friendly to use and it gets into the crux of how to work with the FPGAs and primarily the Vivado tool itself in their toolkit. If people feel complicated with the SOC aspects and working with them using Vitis toolkit, I would at least recommend them to definitely work on the Vivado tool and explore its capabilities, and then understand how to actually improve your use case and how to make your use case FPGA-inclined and make the best out of it. I would recommend looking into AMD's toolkit and exploring options on how to achieve that.

There are a lot of valuable features when it comes to AMD Vivado Design Suite. I primarily appreciate their support for CLI; pretty much all their tools support CLI, which helps me with automating different workflows right from RTL synthesis, implementation, bitstream generation, building the C++, and creating Xcel-Bin packages and other automation tasks.

Nowadays using AI-based agents to perform automation makes much more sense with tools supporting CLI, and AMD Vivado Design Suite is right at the top when it comes to FPGA-based development environments. I have been using these agents to design scripts for me to basically automate all the work that I have been working on. I used to spend more than a week to come up with a script once I have my design ready, and for incremental changes on top of that, this script used to help me fasten the process through rebuilding and regenerating the bitstreams, testing, and other tasks. Now using AI-based integration for generating CLI scripts, it has fastened the process much faster, so I can complete this whole respawning of things within a day.

AMD Vivado Design Suite provides a very powerful FPGA platform. I particularly appreciate the CPU and FPGA integration, which is pretty strong. All the use cases these days require heterogeneous compute where I need multiple kinds of devices in a single place in order to really make the best out of the device and also tune my use case accordingly in order to get the best results. In my work, it is about bringing the best throughput and the best latency out of the device, and all these capabilities and the strong AMD Vivado Design Suite helps me to achieve these goals.

The time saved in development is a bigger factor. I could not go into specific details of how I improved the throughput or latency using an FPGA device as that is more of a design challenge, but when it comes to the tool perspective, for all the reasons that I have mentioned before, the CLI support, pretty strong tool set, and all of that at one place helps me to reduce my development time much and made it a much shorter process.

The UI aspects of the tools could be improved personally. I have been looking at CLI aspects much more as compared to the UI aspects, and I feel at many times I get confused with the options that are actually available in the CLI through the dash parameters to the commands they offer, and finding an equivalent in the UI has always been a hassle for me. A better way to design a UI or documenting it would be helpful.

In summary, having both CLI and UI on a single page and helping users like me find the correlation between a specific option in both CLI and UI and making that workflow much easier is a significant improvement that AMD could possibly work on.

The only disadvantage would be the CLI and UI not being on the same page, and I personally have run into a lot of issues on that aspect. That actually pulled me from giving a perfect rating.

I have been in hardware design for more than five years.

The rest of the tool set is pretty much stable. One other thing to highlight is their PetaLinux support for developing Linux-based SOC applications which run on the FPGA board. It has support for scripting-based automation, and that is another capability which I really appreciate, which I do not think other providers like Altera or Microchip tools support.

When it comes to AI capabilities, I think their Versal device set is a pretty strong contender out there, and pretty much their AI engine and Versal NOC, all of that has been designed for AI use cases, so their capabilities are pretty strong, but I am not entirely sure on their governance or security aspects as I have never thought about it in depth.

AMD Vivado Design Suite is pretty good, particularly with the Versal toolkit. I have been able to use their tools and follow their documentation, tune their example code base for my use cases with the project on my AI accelerator design on the A-LINX board, and I think it is pretty strong.

This interview was pretty interesting, and to be honest, it is my first interview with AI, and I really appreciate the way the questions were asked and how they touched upon the aspects which I was really looking for in this interview, going into the specifics of the tool and the way I used it, and the kind of questions that were asked to gain more insights on my workflow. My overall rating for AMD Vivado Design Suite is eight out of ten.

My main use case for AMD Vivado Design Suite is that I used Vivado and Vivado HLS during a university FPGA project. We were working on a post-quantum cryptography algorithm called Ring-LWE and targeting a Zynq 7000 ZED board.

A specific example of how I used AMD Vivado Design Suite for that FPGA project is that we used Vivado HLS to convert parts of our C implementation into hardware IP. We experimented with different implementation and optimization parameters to find a good balance between latency, performance, and hardware resource usage. Essentially, we tried to accelerate the encryption and decryption algorithm in the FPGA using Vivado.

What I appreciated most about my use case or the project is having the complete FPGA development workflow with AMD Vivado Design Suite. We could generate an IP with Vivado HLS, integrate it into the design, generate the bitstream, and then program and test the actual hardware. The process is notably easier with Vivado HLS.

The best features AMD Vivado Design Suite offers are quite manageable once I understood the workflow, but initially, there was definitely a learning curve, especially understanding the relationship between HLS, IP generation, the Vivado design, synthesis, implementation, and bitstream generation.

The specific features that stood out the most for me in AMD Vivado Design Suite were the HLS pragmas. For example, we implemented the pipeline easily using the HLS pipeline pragma. We accelerated our algorithm and accomplished it quickly with using that pragma.

AMD Vivado Design Suite has impacted me positively, as it made our implementation easier.

One area that could be improved is the learning curve. Vivado is a very powerful tool, but for someone who is new to FPGA development with Vivado, there are many concepts, settings, and different stages in the workflow to understand.

Synthesis and implementation can take considerable time. When I experiment with many different configurations, the iteration cycle can become quite long. Because when I try to develop something and try different things, I need to wait a long time. This could potentially be improved.

In my opinion, AMD Vivado Design Suite can be improved regarding the user interface. I think the user interface is quite good with the UX elements, but it could be improved further.

Regarding needed improvements for the user interface of AMD Vivado Design Suite, I would consider the perspective of new users. When I learned the Vivado user interface, I became really comfortable with it. However, a new person with Vivado probably needs to learn the user interface first before continuing with their work.

I have been using AMD Vivado Design Suite for two years.

AMD Vivado Design Suite is stable in my experience.

AMD Vivado Design Suite's scalability handles my projects well. For example, I implemented direct memory access, chose some settings, and it arranged itself easily.

I have not interacted with customer support for AMD Vivado Design Suite.

Before choosing AMD Vivado Design Suite, I used ISE Design Suite in university. After that, we continued with AMD Vivado Design Suite and have not used another solution since.

My experience with pricing, setup cost, and licensing for AMD Vivado Design Suite is that I did not have any problems with the setup cost and licensing because I used that project in my master's degree at university. Therefore, my university supported those issues and arranged the licensing and setup costs.

I have seen a return on investment from using AMD Vivado Design Suite, particularly in terms of time saved. We used Vivado HLS to develop our program with the C programming language rather than VHDL and Verilog. Vivado HLS converts C programming language code to VHDL and Verilog. This allowed us to quickly implement the new design and accelerate the hardware-friendly functions. Vivado HLS converts the code and saves our time because if we needed to develop that entire architecture with VHDL and Verilog languages, we would probably waste significantly more time.

Regarding AMD Vivado Design Suite's AI capabilities and security, I think there is no problem. I especially trust the output from AMD Vivado Design Suite because it tells me exactly what the problem is with my implementation. It shows me warning information, and when I read that information or error output, I can easily solve my problem and try again. I do not think there is anything else that could be improved with AMD Vivado Design Suite. My advice to others looking into using AMD Vivado Design Suite is that if it is not necessary to continue with VHDL or Verilog programming, I would recommend using Vivado HLS. I would rate my overall experience with AMD Vivado Design Suite as an 8 out of 10.

I used AMD Vivado Design Suite to develop an optimized data acquisition platform using triple modular redundancy for a custom IP in aerospace research.

Previously, we worked on Quartus from Altera, but we migrated to AMD Xilinx FPGAs, which led me to use AMD Vivado Design Suite.

I only used AMD Vivado Design Suite for educational purposes, so there was no billing involved.

I really value the speed of use of the IP Integrator in AMD Vivado Design Suite.

I would love to see fewer software bugs, better documentation, and more intuitive use cases to improve AMD Vivado Design Suite.

In the design suite, I have always encountered a problem with uploading programs through Vitis IDE.

The design suite is very effective for its intended purpose, but it has many software bugs and is sometimes counter-intuitive, which makes the workflow worse. This is why I gave it a rating of 7 out of 10.

Regarding one bug, my mentor searched for information or reported it to the Vivado team, but he did not receive a response.

There are no improvements needed for AMD Vivado Design Suite that I have not already mentioned.

I advise others looking into using AMD Vivado Design Suite to approach it with patience and be prepared for a steep learning curve. My overall rating for this product is 7 out of 10.

My primary use case for AMD Vivado Design Suite is RTL development in VHDL targeting AMD FPGAs and SoCs. I also use it extensively for system integration, combining RTL modules with designs generated through High-Level Synthesis (HLS) and MATLAB/Simulink.

I use Vivado across a wide range of projects. For example, I have developed FPGA-based prototypes for industrial automation systems and recently automated the integration of third-party IP cores into FPGA-based subsystems. Vivado is the central tool in my FPGA development workflow, from RTL implementation to final device integration.

AMD Vivado Design Suite has had a positive impact on our organization because it is the reference implementation environment for AMD FPGA and SoC devices. It represents the final integration stage of our FPGA development flow, where all hardware components come together before deployment.

Its stability and robustness are essential because every project ultimately passes through Vivado for synthesis, implementation, timing analysis, and bitstream generation.

One of the biggest benefits is the quality of the reports and diagnostics generated during implementation. Vivado provides detailed timing reports, implementation statistics, and design rule checks that help us identify problems early. However, interpreting some warnings and timing reports can still require significant experience, and determining the best corrective action is not always straightforward.

The most valuable aspect of AMD Vivado Design Suite is its comprehensive low-level implementation flow together with the ML-based implementation strategies introduced in recent releases. These capabilities help improve timing closure and provide better implementation results for complex FPGA designs.

When working on timing closure and Static Timing Analysis (STA), these implementation strategies are particularly valuable because they often improve placement and routing decisions while helping achieve timing requirements more efficiently.

Another important feature is Vivado's infrastructure for developing reusable IP cores compliant with the IP-XACT standard. This greatly simplifies subsystem integration and enables reusable hardware architectures across multiple projects.

I also appreciate the flexibility offered by Vivado during synthesis and implementation. The ability to select different optimization strategies and apply custom implementation constraints allows developers to tailor the design flow according to the specific requirements of each FPGA project.

Another valuable capability is interoperability with third-party tools. I have extensive experience using Synopsys Synplify Premier, particularly for space applications involving Triple Modular Redundancy (TMR), Clock Domain Crossing (CDC) verification, and complex FPGA architectures. Integration with tools such as QuestaSim, ModelSim, MATLAB, and Vitis enables a complete and flexible development workflow.

One area where AMD Vivado Design Suite could improve is helping developers better understand the root causes of implementation problems. While Vivado provides excellent support for VHDL, Verilog, and SystemVerilog development, physical implementation remains highly dependent on the engineer's experience.

An AI assistant capable of analyzing timing reports, constraints, placement decisions, routing congestion, and implementation results could significantly improve developer productivity, especially for high-frequency and high-performance FPGA designs.

Another improvement would be better support for integrating domain-specific scripting languages into subsystem generation. The recent support for P4 is a step in the right direction, but integrating additional scripting languages and design-generation frameworks would make it much easier to automate subsystem creation and third-party IP integration.

Finally, implementation times can become quite long on very large designs. Although FPGA devices continue to grow in complexity, reducing synthesis and implementation times would significantly improve overall development productivity.

I have been using AMD Vivado Design Suite for over 20 years.

In terms of stability, I find that the latest version of AMD Vivado Design Suite is quite stable, especially when using the command line interface, allowing for fast operations without a GUI. I have not encountered crashes or problems, although using important constraints such as the DCP format during design is necessary.

Scalability within AMD Vivado Design Suite is inherent, as one can manage projects in various ways, importing half products such as EDIF and RTL for completion within Vivado, as well as generating projects and integrating semi-products from third-party tools without issues, although middle formats for low-level integration are required.

My experience with customer support for AMD Vivado Design Suite has been very positive. I have been in direct contact with AMD and received valuable advice for past issues, and I find that the community provides a wealth of information on resolving various problems related to constraints and TCL scripting issues at a low level.

Before using AMD Vivado Design Suite, I worked with ISE for the previous FPGA versions, and I switched to Vivado because it is essential for the latest products such as Ultrascale and Versal, making this transition mandatory.

Currently, I do not evaluate other options when it comes to using AMD Vivado Design Suite for physical implementation. However, I do consider switching to a tool with greater synthesis capabilities from the Synopsys family in the near future for synthesis purposes.

To others considering using AMD Vivado Design Suite, I recommend that it can be a fantastic tool for various applications, emphasizing the importance of integrating with third-party software. I previously mentioned that improving the interface with external tools such as P4 scripts for the development of various applications is essential. Although the code generated from third-party tools is often not optimal, Vivado does provide optimization capabilities for that code, so it would be beneficial to improve the generation quality of code from external tools. I would rate my overall experience with AMD Vivado Design Suite as a 10.

My main use case for AMD Vivado Design Suite is FPGA development. I used it to develop a game where I designed a game on a Nexys board, and I also used it for an asynchronous communication system on an RT-AXA7 board.

The best features AMD Vivado Design Suite offers include integrated IPs, which is the best thing. If you design anything, you can see everything in AMD Vivado Design Suite, including the schematic view, timing analysis, simulation waves, and tools to test the device internally.

I find myself using simulation and schematic the most because whatever I developed, I need to test, so I used the simulation and schematic mostly, along with the performance analysis tools as well.

AMD Vivado Design Suite has positively impacted my organization because it helped very well by having everything in one tool. You don't need to go for another tool for simulation. While we have some other tools as well, for development and simulation, you have to use one tool, and in AMD Vivado Design Suite, everything is included, which saved me time and made it easy to operate.

AMD Vivado Design Suite could be improved regarding speed. Sometimes it will take so much time to show the schematics and performance analyzing tool.

I have been using AMD Vivado Design Suite for the last two years.

I estimate that I can save ten days on a six-month project by having everything in one tool.

If you are developing any device using AMD Vivado Design Suite, you can check from the beginning to the end of the entire device development cycle.

I gave AMD Vivado Design Suite a rating of six out of ten because while we have everything, it is very slow, and it is also not free; it is licensed.

Regarding AMD Vivado Design Suite's AI capabilities, I think its governance and security are good. Regarding AMD Vivado Design Suite's AI capabilities, I believe the accuracy and reliability of output are good.

I am not sure which cloud provider we are using. I have no experience with pricing, setup cost, and licensing. My overall review rating for AMD Vivado Design Suite is six out of ten.

My main use case for AMD Vivado Design Suite involves competitions where we use Genesis 2 boards and the Kintex-7 IC, which is a pure FPGA. It is important because in the market, many FPGAs consist of products by Xilinx AMD. We use AMD Vivado Design Suite when we want to program this FPGA and boards.

In my experience, the best features AMD Vivado Design Suite offers include being easy to use and not complicated, thanks to the Flow Navigator that allows you to access anything and reach anything on the same screen. You are coding on the right, can synthesize, implement, and reach the source easily. Its text editor is greater than the other EDA tools I use, which are Vivado, Libero, Microchip Libero, and Altera Quartus. When I compare it to the other two products, I find AMD Vivado Design Suite better, although I am currently using VS Code and do not even open the AMD Vivado Design Suite text editor because we are writing Tcl, which automates implementation, designs, and design flow. AMD Vivado Design Suite is easier to learn than other EDA tools, although I am not using the AMD Vivado Design Suite text editor currently.

AMD Vivado Design Suite has positively impacted our organization because it is a great tool that makes jobs easier. Additionally, AMD provides versatile IPs that allow you to create your block design, which makes work faster. In AMD Vivado Design Suite, XSim is a simulation software that comes embedded, so we do not need any other simulation tools. It also improves work quality due to its good error feedback, allowing you to return these errors and fix your code easily in the programming process.

Regarding features of AMD Vivado Design Suite, if AMD adds AI, it could enhance the design suite even more because there is currently no AI chat; you must enter VS Code or use the cloud or other AI tools.

AMD Vivado Design Suite can be improved by adding AI.

I have been working in my current field for approximately two years.

AMD Vivado Design Suite is stable in my experience.

AMD Vivado Design Suite's scalability is very good, as it can handle larger or more complex projects well. Currently, we are designing a chip and need to prototype on the FPGA in Genesis boards that include Kintex-7.

I have not experienced any support issues with AMD Vivado Design Suite, but our other engineers and colleagues have reached out for support regarding some issues, and I think their return is very good and the support team is very good.

I did not previously use a different solution before AMD Vivado Design Suite because, depending on the project requirements, if your project needs a Microchip FPGA, you use Libero, and if your project needs a Xilinx FPGA, you use Xilinx. It is not a matter of switching; you simply use what your project needs.

I have seen a return on investment from using AMD Vivado Design Suite because it required fewer people due to its ease of use. You can adapt yourself very easily, and it has improved the quality of our work because its error feedback is very good, allowing for easy error correction and programming.

I believe the pricing, setup cost, and licensing for AMD Vivado Design Suite are good, although I do not have any idea of this because my company solved this problem.

I did not evaluate other options before choosing AMD Vivado Design Suite because I only had one option when I started, which was the Xilinx card, so I had to choose AMD Vivado Design Suite.

I would rate AMD Vivado Design Suite a 7.5 out of 10 because I am currently not using the tool or GUI; I am using Tcl and just writing RTLs.

Regarding AMD Vivado Design Suite's AI capabilities, I think it is a very reliable tool because I trust it.

My advice to others looking into using AMD Vivado Design Suite is to first learn digital design basics and logic basics. You should study them before buying some kits for education, such as Basys 3, or others such as GOWIN if you want something cheaper. You can easily find tutorials on YouTube about VHDL, Verilog, or digital design. Do not directly go into AMD Vivado Design Suite because it can be very complex for first-time users; first, you should understand the basics such as digital design fundamentals and signals and systems.

I have covered everything regarding AMD Vivado Design Suite, and it is sufficient.