AMD Vivado Design Suite played a major role in FPGA integration. It provided a complete design flow of RTL development, bitstream generation, synthesizing the hardware design, performing implementation, analyzing timing, and verifying the timing diagram. One of the most important roles was that I got the IP of my CNN, but I had to integrate it with all the other components including Artix-7, interconnects, DMAs, and other components. I used those components. The most important and valuable task of AMD Vivado Design Suite was its optimization. For example, if I got an FPGA board of Artix-7 20T, and I was facing the same problem, I got lots of DSPs, about 220 DSPs, but when I synthesized the program, the DSPs went out of the range. They demanded 300 flip-flops, about 80 above its maximum range it can reach. I found an option in AMD Vivado Design Suite where I can easily degrade and optimize my code so that it would get for about 220, less than 220 DSPs, so that they could be utilized even better. The best feature AMD Vivado Design Suite offers in my experience is its automatic optimization. I can optimize things, including flip-flops and timing. For example, if I am working on an RTOS project and I want real-time performance, it must be a timing issue. AMD Vivado Design Suite provides me an automated, real-time timing diagram, and that could fix any issues in the RTL design that could affect the timing.
