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In addition to supporting standard HDLs, ModelSim increases design
quality and debug productivity. ModelSim’s award-winning Single Kernel
Simulator (SKS) technology enables transparent mixing of VHDL and
Verilog in one design. Its architecture allows platform-independent
compile with the outstanding performance of native compiled code.
The graphical user interface is powerful,
consistent, and intuitive. All windows update automatically following
activity in any other window. For example, selecting a design region in
the Structure window automatically updates the Source, Signals, Process,
and Variables windows. You can edit, recompile, and re-simulate without
leaving the ModelSim environment. All user interface operations can be
scripted and simulations can run in batch or interactive modes. ModelSim
simulates behavioral, RTL, and gate-level code, including VHDL VITAL
and Verilog gate libraries, with timing provided by the Standard Delay
Format (SDF).
Software package for designing, scheduling, distributing and displaying of any information on public displays.
Cavium, Huawei Technologies, IBM, IN2P3, JDSU, Liquid Computing Corporation, Marconi Communications, NVIDIA, Pegatron, Polycom, Tait Electronics, VeriSilicon, Tait Communications, Faraday Technology
Wilson Research Group
Aethercomm Inc., Andrew Ferencz Consulting, Anritsu, Cool Earth Solar Inc., Dynapar, Ellett Valley Group, Pelagic Pressure Systems Inc.